# auto-arch-tournament > An autonomous agent loop that proposes, implements and verifies microarchitectural improvements to a SystemVerilog RV32IM CPU using formal verification, cosim and FPGA place-and-route. auto-arch-tournament is an open-source research loop, published by FeSens on GitHub, that points a coding agent at a SystemVerilog RV32IM CPU. Each round the agent proposes a microarchitectural hypothesis, implements it in an isolated git worktree, and runs it through a gated verification pipeline. Only hypotheses that beat the current champion on CoreMark/MHz are merged. It also underlies HWE Bench, a benchmark for LLM hardware development on RISC-V. ## What It Is It is an orchestrated, hardcoded evaluation-and-evolution framework for CPU design. Each core lives under `cores//` with its own RTL, cocotb tests, experiment log, `core.yaml`, and `LESSONS.md`. `make loop TARGET=` runs the loop for one core on a dedicated `core-` branch in its own worktree, so several cores can evolve in parallel. The orchestrator never merges to `main`; each core's evolution is a single reviewable PR diff. ## How a Round Works A hypothesis agent writes a YAML hypothesis against a JSON schema, using the source RTL, recent log entries, lessons, and optional core philosophy. An implementation agent then edits only the core's `rtl/` and cocotb tests. The eval pipeline runs Verilator lint, Yosys synthesis, a benchmark build, cosim build, riscv-formal, Verilator cosim against a Python ISS, and 3-seed FPGA place-and-route with CoreMark. The first failing step short-circuits the round. A scribe agent then records a lesson for later rounds. The highest-fitness slot above the champion merges. ## Verification and Guardrails - riscv-formal symbolic checks against RV32IM (about 105 checks at NRET=2). - Verilator cosim with random bus stalls, comparing RVFI output to a Python ISS. - Median Fmax across 3 seeds on a Gowin GW2A-LV18 (Tang Nano 20K) combined with CoreMark iterations per cycle for fitness. - Independent CoreMark CRC validation. - A path sandbox that rejects rounds where the agent touched anything outside its core's `rtl/` and `test/test_*.py`. ## Reported Results The README reports a run of 73 hypotheses over 9h 51m that produced `cores/v1/` from `cores/baseline/`. In that run, 10 were accepted and 63 rejected. The champion went from 301 to 577 iter/s (2.23 to 2.91 CoreMark/MHz), which the author compares with VexRiscv's published 2.30 CoreMark/MHz. ## Setup Path Setup is macOS only for now. `bash setup.sh` installs Verilator, OSS CAD Suite, the RISC-V cross compiler, and Python dependencies into `.toolchain/`. A coding-agent CLI is also needed: Codex by default, or Claude Code via `AGENT=claude`. The repository is licensed under Apache 2.0. ## Features - Autonomous hypothesis-implement-verify loop for CPU microarchitecture - Multi-core layout with per-core git worktrees and branches - Parallel slots per round - riscv-formal symbolic verification - Verilator cosim against a Python ISS - 3-seed FPGA place-and-route fitness on Tang Nano 20K (GW2A-LV18) - CoreMark CRC validation - Path sandbox restricting agent edits - Scribe-maintained LESSONS.md and experiment log - Progress reports and charts - Selectable coding agent (Codex or Claude Code) ## Integrations Codex CLI, Claude Code, Verilator, Yosys, nextpnr-himbaechel, riscv-formal, cocotb, SymbiYosys, bitwuzla, GitHub CLI ## Platforms MACOS, API, CLI ## Pricing Open Source ## Links - Website: https://github.com/FeSens/auto-arch-tournament - Repository: https://github.com/FeSens/auto-arch-tournament - EveryDev.ai: https://www.everydev.ai/tools/auto-arch-tournament